1. Field of Invention
The present invention relates to a memory controller. More particularly, the present invention relates to a converter and an application program for converting an extended data output dynamic random access memory (EDO DRAM) command into a synchronous dynamic random access memory (SDRAM) command.
2. Description of Related Art
Due to the rapid progression of manufacturing technologies, new types of memory are produced while older types of memory rapidly become obsolete. Hence, the versions of many controller application systems that use older types of memory must either be revised or else production stopped altogether. Although extended data output dynamic random access memory (EDO DRAM) is still manufactured, decrease in production quantity has lead to a price hike that may eventually lead to an end to its production. Ultimately, the price of the application system using this type of memory is increased and the life cycle of such a system is uncertain.
Accordingly, one object of the present invention is to provide a memory command converter and its application system so that an application system for using extended data output dynamic random access memory (EDO DRAM) may also use a mainstream memory system such as a synchronous dynamic random access memory (SDRAM) through a memory command converter. Thus, cost of the application system is reduced while the working life of the application system is extended.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a memory command converter. The memory converter is capable of converting a first command control signal from a control chip for controlling EDO DRAM into a second command control signal acceptable by a SDRAM chip. The memory converter includes a mode control selection storage device, a command control circuit and a clocking control circuit. The mode control selection storage device is coupled to the control chip for receiving and holding the mode control selection value from the SDRAM chip. The command control circuit is coupled to the mode control selection storage device, the control chip and the SDRAM chip. The command control circuit sets the operating mode of the SDRAM chip and converts the first command control signal from the EDO DRAM into the second command control signal acceptable to the SDRAM chip according to the mode control selection value in the mode control selection storage device. The clocking control circuit is coupled to an external clocking device, the command control circuit, the control chip and the SDRAM chip. The clocking control circuit receives clocking signals from the clocking device and redirects to the command control circuit, the control chip and the SDRAM chip to serve as a synchronizing pulse.
In the preferred embodiment of this invention, one end of the memory command converter includes I first row addresses and J first column addresses that communicate with the control chip through the first command control signal. The other end of the memory command converter includes K second row addresses, L second column addresses and M bank addresses that communicate with the SDRAM chip through the second command control signal. There are three modes altogether. If L greater than J and N=K+Mxe2x88x92I such that N is a whole number greater than zero, the I first row addresses are sent directly from the command control circuit to the I second row addresses and the bank addresses as soon as the I first row addresses are received. Furthermore, according to the setting provided by the mode control selection storage device, the levels of another N second row addresses and bank addresses are determined so that the page among the 2N simulated pages of the SDRAM chip can be selected. As soon as the J first column addresses are received, the addresses are directly transferred to the J second column addresses and the Lxe2x88x92J second column addresses are fixed to a low level.
In a second conversion mode according to this invention, if N=(K+L+M)xe2x88x92(Ixe2x88x92J) and N is a whole number greater than zero, the I first row addresses are latched and held as soon as the command control circuit receives the I first row addresses. On receiving the J first column addresses, the command control circuit redistributes the I first row addresses and the J first column addresses and re-transmits the addresses to the (I+Jxe2x88x92L) second row addresses and bank addresses. According to the setting provided by the mode control selection storage device, the N second row addresses and bank addresses is determined so that the page among the 2N simulated pages of the SDRAM chip can be selected. Finally, the distributed L second column addresses are transmitted.
In a third conversion mode according to this invention, if L+M=J, Kxe2x88x92I=N and N is a whole number greater than zero, the I first row addresses are directly transmitted to the I second row addresses continuously 2M times, as soon as the command control circuit receives the I first row addresses. According to the mode control selection value, the levels of the N second row addresses are determined so that the page among the 2N simulated pages of the SDRAM chip can be selected. In the meantime, the 0xcx9c2Mxe2x88x921 bank address values are sequentially transmitted so that various banks in the SDRAM chip are triggered. On receiving the J first column addresses, the J first column addresses are transmitted to the L second column addresses and the M bank addresses.
In addition, the memory command converter according to this invention may be applied to various application systems as long as the application system includes a control chip capable of controlling an EDO DRAM chip and a clocking generator. With the addition of the memory command converter, an EDO DRAM chip may be used alternately with a main stream SDRAM chip. Hence, the manufacturing cost of the application system is reduced and the working life of the application system is extended.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.